An Area-Efficient FPGA Implementation of a Disparity Estimation Scheme for Real-TimeCompression of IP Images
نویسندگان
چکیده
The interest for real three dimensional displays has been revived over the past few years, and the high resolution images that capturing and reproducing of 3D imagery demands, must be addressed with an efficient compression scheme. An area-efficient hardware implementation of a real-time disparity estimation scheme targeted to Integral Photography 3D images is presented, exploiting the inherent redundancy of Integral Photography images, coping with the increased bandwidth that this technology requires.
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تاریخ انتشار 2004